1. Field of the Invention
The present disclosure generally relates to the field of semiconductor manufacturing, and, more particularly, to the formation of an interconnect structure directly contacting a circuit element with the first metallization level.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a great number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
Due to the continuous reduction of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density, also increases, thereby requiring an even larger increase in the number of electrical connections to provide the desired circuit functionality, since the number of mutual connections between the circuit elements typically increases in an over-proportional way compared to the number of circuit elements. Therefore, the number of stacked metallization layers usually increases as the number of circuit elements per chip area becomes larger, while nevertheless the sizes of individual metal lines and vias are reduced. Due to the moderately high current densities that may be encountered during the operation of advanced integrated circuits, and owing to the reduced feature size of metal lines and vias, semiconductor manufacturers are increasingly replacing the well-known metallization materials, such as aluminum, with a metal that allows higher current densities and, hence, permits a reduction in the dimensions of the interconnections. Consequently, copper and alloys thereof are materials that are increasingly used in the fabrication of metallization layers due to the superior characteristics in view of resistance against electromigration and the significantly lower electrical resistivity compared to, for instance, aluminum. Despite these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper readily diffuses in a plurality of well-established dielectric materials, such as silicon dioxide, wherein even minute amounts of copper, accumulating at sensitive device regions, such as contact regions of transistor elements, may lead to a failure of the respective device. For this reason, great efforts have to be made to reduce or avoid any copper contamination during the fabrication of the transistor elements, thereby rendering copper a less attractive candidate for the formation of contact plugs, which are in direct contact with respective contact regions of the circuit elements. The contact plugs provide the electrical contact of the individual circuit elements to the first metallization layer, which is formed above an interlayer dielectric material that encloses and passivates the circuit elements.
Consequently, in advanced semiconductor devices, the respective contact plugs are typically formed of a tungsten-based metal in an interlayer dielectric stack, typically comprised of silicon dioxide, that is formed above a corresponding bottom etch stop layer, which may typically be formed of silicon nitride. Due to the ongoing shrinkage of feature sizes, however, the respective contact plugs have to be formed within respective contact openings with an aspect ratio which may be as high as approximately 8:1 or more, wherein a diameter of the respective contact openings may be 0.1 μm or even less for transistor devices of the 65 nm technology. The aspect ratio of such openings is generally defined as the ratio of the depth of the opening to the width of the opening. Consequently, the resistance of the respective contact plugs may significantly restrict the overall operating speed of highly advanced integrated circuits, even though a highly conductive material, such as copper or copper alloys, may be used in the metallization layers. Moreover, sophisticated etch and deposition techniques may be required for forming the contact plugs, as will be described with reference to FIGS. 1a and 1b in more detail.
FIG. 1a schematically illustrates a top view of a portion of a semiconductor device 100. The semiconductor device 100 comprises a substrate (not shown in FIG. 1a) above which is formed a semiconductor layer (not shown) in and above which circuit elements, such as a transistor and the like, are formed. For convenience, a circuit element in the form of a transistor 150 is illustrated. The transistor 150 may comprise a gate electrode structure 151, sidewalls of which may be covered by a spacer element 152. Laterally adjacent to the gate electrode structure 151, an active region in the form of drain and source regions 153 are provided which may be, in addition to a channel region (not shown), located below the gate electrode structure 151 and may represent an active region in the corresponding semiconductor layer. The active region may be defined by an isolation structure 102, above which a portion of the gate electrode structure 151 may be positioned, thereby defining a contact region 154 in contact with a contact plug or contact element 110. Similarly, one or more contact elements 111 may be provided in the drain or source region 153, wherein, for convenience, only one such contact element 111 is illustrated. It should be appreciated that the contact elements 110, 111 are typically formed in an appropriate interlayer dielectric material which, for convenience, is not shown in FIG. 1a. 
FIG. 1b schematically illustrates a cross-sectional view along the line 1b as shown in FIG. 1a, wherein the semiconductor device 100 is illustrated in a further advanced manufacturing stage. As shown, the semiconductor device 100 comprises a substrate 101 which represents any appropriate carrier material, such as a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. A silicon-based semiconductor layer 103 is formed above the substrate 101, and the isolation structure 102, for instance, in the form of a trench isolation, defines an active region 104 in which are positioned the drain and source regions 153, i.e., respective dopant concentrations, to define respective PN junctions with the remaining portion of the active region 104. Furthermore, metal silicide regions 155 may be formed in the drain and source regions 153, thereby defining a contact region thereof, and on the gate electrode structure 151, including the contact portion 154, thereby also defining a respective contact region for the gate electrode structure 151. Furthermore, the semiconductor device comprises an interlayer dielectric material 115 which typically comprises two or more dielectric layers, such as the layers 115A, which may represent a contact etch stop layer comprised of silicon nitride, and a second dielectric material 115B, for instance, provided in the form of a silicon dioxide material. Typically, a thickness 115T of the interlayer dielectric material 115 is in the range of several hundred nanometers so as to obtain a sufficient distance between the gate electrode structure 151 and a first metallization layer 120 in order to maintain the parasitic capacitance at a required low level. Consequently, the contact element 111 connecting to the drain or source region 153 may have a moderately high aspect ratio, since the lateral size thereof is substantially restricted by the lateral dimension of the drain and source regions 153, while the depth of the contact element 111 is determined by the thickness 115T of the interlayer dielectric material 115. On the other hand, the contact element 110 only has to extend down to the top surface of the gate electrode structure 151, i.e., to the contact portion 154, while also the lateral dimension of the contact element 110 may be different compared to the element 111, depending on the size and shape of the contact portion 154. The contact elements 110, 111 typically comprise a barrier material in the form of a titanium liner 112, followed by a titanium nitride liner 113, while the actual fill material 114 may be provided in the form of a tungsten material.
The metallization layer 120 typically comprises an etch stop layer 123, for instance, in the form of silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like, on which may be formed an appropriate dielectric material, such as a low-k dielectric material having a relative permittivity of 3.0 or less. Moreover, respective metal lines 121, 122 are formed in the dielectric material 124 and connect to the contact elements 110, 111, respectively. The metal lines 121, 122 may comprise a copper-containing metal in combination with an appropriate barrier material 125, such as a material comprising tantalum, tantalum nitride and the like. Finally, a cap layer 126 is typically provided to confine the copper material in the metal lines 121, 122, which may be accomplished on the basis of dielectric materials such as silicon nitride, silicon carbide and the like.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1b may comprise the following processes. After forming the circuit element 150 on the basis of well-established techniques in accordance with design rules of the respective technology node, which includes forming an appropriate gate insulation layer (not shown) and patterning the same along with the gate electrode structure 151 by sophisticated lithography and etch techniques, the drain and source regions 153 may be formed by ion implantation, using the spacer structure 152 as an appropriate implantation mask. After any anneal cycles, the metal silicide regions 155 are formed and the interlayer dielectric material is deposited, for instance, by forming the contact etch stop layer 115A, followed by the deposition of silicon dioxide material on the basis of plasma enhanced chemical vapor deposition (PECVD) techniques. After planarizing the resulting surface topography of the silicon dioxide material, a photolithography sequence may be performed on the basis of well-established recipes, followed by anisotropic etch techniques for forming contact openings extending through the interlayer dielectric material 115 so as to connect to the gate electrode structure 151 and the drain and source regions 153. During the respective etch process, sophisticated patterning regimes may be required due to the high aspect ratio of the corresponding contact opening, in particular for the contact element 111. During the complex etch sequence, the layer 115A may be used as an etch stop layer for etching the silicon dioxide material 115B, after which a further etch process may be performed in order to finally expose the contact regions in the drain and source regions 153 and the gate electrode structure 151, i.e., the metal silicide regions 155. Next, the titanium nitride liner 112 is formed on the basis of, for instance, physical vapor deposition, such as sputter deposition. The term “sputtering” describes a mechanism in which atoms are ejected from a surface of a target material that is itself hit by sufficiently energetic particles. Sputtering has become a frequently used technique for depositing titanium, titanium nitride and the like. Due to the superior characteristics compared to, for instance, CVD techniques with respect to controlling layer thickness, when forming compounds such as titanium nitride and the like, additionally, exposed surfaces may be inherently cleaned by performing a sputtering without providing a deposition species. Thus, after forming the titanium nitride liner 112, the titanium layer 113 may also be formed by sputter deposition wherein, however, the high aspect ratio, in particular in the contact opening corresponding to the contact element 111, may result in an increased layer thickness at sidewall portions so as to accomplish a reliable coverage of all exposed surface portions of the contact opening. Thereafter, the tungsten material 114 may be deposited by chemical vapor deposition (CVD) in which tungsten hexafluorine (WF6) is reduced in a thermally activated first step on the basis of silane and is then converted into tungsten in a second step on the basis of hydrogen. During the reduction of the tungsten on the basis of hydrogen, a direct contact to silicon dioxide of the layer 115B is substantially prevented by the titanium liner 113 in order to avoid undue silicon consumption from the silicon dioxide. On the other hand, the silicon nitride layer 112 may enhance the adhesion of the titanium liner 113, thereby enhancing the overall mechanical stability of the contact elements 110, 111. Thus, the increased aspect ratio of the contact element 111 may result in a highly complex etch sequence and a subsequent deposition of the liners 112, 113 which may result in a reduced effective cross-sectional area of the contact element 111, thereby increasing the overall series resistance thereof. On the other hand, any non-uniformities during the complex patterning process may result in a contact failure, which may represent one of the dominant factors that contribute to the overall yield loss.
Thereafter, the metallization layer 120 may be formed by depositing the etch stop layer 123 followed by the deposition of the dielectric material 124. Next, respective trenches are formed in the dielectric material 124 according to well-established single damascene strategies. Next, metal lines 121, 122 may be formed by depositing a barrier layer 125 and filling in a copper-based material, for instance, on the basis of electroplating, which may be preceded by the deposition of a copper seed layer. Finally, any excess material may be removed, for instance by chemical mechanical polishing (CMP), and the cap layer 126 may be deposited.
Consequently, the contact structure of the semiconductor device 100 comprises high aspect ratio contacts, such as the contact element 111, resulting in a complex patterning and deposition regime, thereby increasing the probability for reduced production yield, while also contributing to increased resistance and thus reduced electrical performance.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.